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| CXL5506M/P CMOS-CCD 1H Delay Line for PAL Description The CXL5506M/P are CMOS-CCD delay line ICs that provide 1H delay time for PAL signals including the external low-pass filter. Features * Single 5V power supply * Low power consumption 95mW (Typ.) * Built-in peripheral circuits Functions * 1130-bit CCD register * Clock driver * Auto-bias circuit * Input clamp circuit * Sample-and-hold circuit Structure CMOS-CCD CXL5506M 8 pin SOP (Plastic) CXL5506P 8 pin DIP (Plastic) Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD 6 V * Operating temperature Topr -10 to +60 C * Storage temperature Tstg -55 to +150 C * Allowable power dissipation PD CXL5506M 350 mW CXL5506P 480 mW Recommended Operating Condition (Ta = 25C) Supply voltage VDD 5 5% V Recommended Clock Conditions (Ta = 25C) * Input clock amplitude VCLK 0.3 to 1.0 Vp-p (0.5Vp-p typ.) * Clock frequency fCLK 17.734475 MHz * Input clock waveform Sine wave Blook Diagram and Pin Configuration (Top View) AB VDD Input Signal Amplitude VSIG 575mVp-p (Max.) (at internal clamp condition) VG1 CLK 5 Timing circuit Clock driver Bias circuit (A) Output circuit Bias circuit (B) 4 8 7 6 Auto-bias circuit Bias circuit CCD (1130bit) (S/H 1bit) Clamp circuit 1 2 3 VG2 OUT Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- VSS IN E90632B7X-PS CXL5506M/P Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol IN VG2 OUT VSS CLK VG1 VDD AB I/O I I O -- I O -- O Description Signal input Gate bias 2 DC input Signal output GND Clock input Gate bias 1 DC output Power supply (5V) Auto-bias DC output 600 to 200k > 10k 40 to 500 Impedance > 10k at no clamp Description of Pin 2 (VG2) Control of input signal clamp condition 0V ........ Sync tip clamp condition 5V ........ Center bias condition Center biased to approx. 2.1V by means of the IC internal resistance (approx. 10k). In this mode, the input signal is limited to APL 50% and the maximum input signal amplitude is 200mVp-p. Input waveform Output waveform Clamp level -2- CXL5506M/P Electrical Characteristics (Ta = 25C, VDD = 5V, fCLK = 17.734475MHz, VCLK = 500mVp-p, sine wave) See "Electrical Characteristics Test Circuit" Item Supply current Low frequency gain Symbol IDD GL Test condition -- 200kHz, 500mVp-p, sine wave 200kHz 4.43MHz, 150mVp-p, sine wave 5-staircase wave (See Note 4) 5-staircase wave (See Note 4) No signal input 50% white video signal (See Note 6) SW condition 1 a a b 2 a a Min. Typ. Max. Unit Note 3 -- b 10 -2 19 0 28 2 mA dB 1 2 Frequency response fR b b -2 -1 0 dB 3 c d d f e a a b a c c a d 0 0 -- 52 3 3 -- 56 5 5 % degree Differential gain Differential phase S/H pulse coupling S/N ratio DG DP CP SN 4 4 5 6 350 mVp-p -- dB Notes (1) This is the IC supply current value during clock and signal input. (2) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin. GL = 20 log OUT pin output voltage [mVp-p] [dB] 500 [mVp-p] (3) Indicates the dissipation at 4.43MHz in relation to 200kHz. From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p, 4.43MHz sine wave is fed to same, calculation is made according to the following formula. fR = 20 log OUT pin otuput voltage (4.43MHz) [mVp-p] [dB] OUT pin output voltage (200kHz) [mVp-p] -3- CXL5506M/P (4) In figure below, differential gain (DG) and differential phase (DP) are tested with a vector scope when the 5-staircase wave is fed. 150mV 350mV 500mV 150mV 1H 64s Input waveform (5) The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. Test value (mVp-p) (6) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in BPF 100kHz to 5MHz, Sub Carrier Trap mode. 175mV 325mV 150mV 1H 64s Input waveform Clock 4fsc (17.734475MHz) sine wave 0.3 to 1.0Vp-p (0.5Vp-p typ.) -4- Electrical Characteristics Test Circuit CLK 4fSC (17.734475MHz) 0.5Vp-p sine wave 3.3 1000p 200kHz 500mVp-p sine wave 1000p 1 8 AB 9V b IN VG2 2 3 4 2.1k Note 1) SW3 c 1 1M 1000p SW2 a b d BPF LPF Note 2) x3 x3 OUT VSS 1 VDD CLK VG1 a 7 6 5 0.1 a 200kHz 150mVp-p sine wave b Oscilloscope Spectrum analyzer -5- Note 1) 5V 0 -3 -50 SW1 4.43MHz 150mVp-p sine wave c Vector scope Noise meter 5-staircase wave d Note 2) [dB] LPF frequency response [dB] 0 -3 BPF frequency response 50% white video signal e f -50 7M Frequency [Hz] 17.7M 200 7M 17.7M Frequency [Hz] CXL5506M/P Application Circuit 4fSC (17.734475MHz) 0.5Vp-p sine wave 5V 3.3 1000p 1 8 12 7 6 10 5 1000p 0.1 -6- 1 2 3 4 330k 1 470 LPF (Inverted signal) 560k 1k 27p Transistor used PNP: 2SA1175 Delay time 190ns (Non-inverted signal) Input 1 5V 2200 1M Output 2200 2200 (Non-inverted signal) Transistor used NPN: 2SC2785 (ex. TH328LNLS-2620 Toukou made) CXL5506M/P Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXL5506M/P Example of Representative Characteristics Supply current vs. Ambient temperature 30 Low frequency gain vs. Ambient temperature 2 20 Low frequency gain [dB] 0 20 40 60 80 1 Supply current [mA] 0 -1 10 -20 -2 -20 0 20 40 60 80 Ambient temperature [C] Ambient temperature [C] Frequency response vs. Ambient temperature 0 10 Differential gain vs. Ambient temperature 8 Frequency response [dB] -1 Differential gain [%] 0 6 4 -2 2 -3 -20 20 40 60 80 0 -20 0 20 40 60 80 Ambient temperature [C] Ambient temperature [C] Supply current vs. Supply voltage 30 2 Low frequency gain vs. Supply voltage 20 Low frequency gain [dB] 5 Supply voltage [V] 5.25 1 Supply current [mA] 0 -1 10 4.75 -2 4.75 5 Supply voltage [V] 5.25 -7- CXL5506M/P Frequency response vs.Supply voltage 0 10 Differential gain vs. Supply voltage 8 Frequency response [dB] -1 Differential gain [%] 6 4 -2 2 -3 4.75 5 Supply voltage [V] 5.25 0 4.75 5 Supply voltage [V] 5.25 Frequency response 2 0 Gain [dB] -2 -4 -6 10k 100k Frequency [Hz] 1M 10M -8- CXL5506M/P Package Outline CXL5506M Unit: mm 8PIN SOP (PLASTIC) + 0.4 6.1 - 0.1 + 0.4 1.85 - 0.15 8 5 0.15 + 0.2 0.1 - 0.05 + 0.3 5.3 - 0.1 7.9 0.4 1 0.45 0.1 4 + 0.1 0.2 - 0.05 1.27 6.9 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-8P-L01 SOP008-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.1g CXL5506P 8PIN DIP (PLASTIC) 8 5 7.62 + 0.3 6.4 - 0.1 + 0.4 9.4 - 0.1 + 0.1 0.05 0.25 - 0 to 15 EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.5g 1 2.54 4 0.5 0.1 1.2 0.15 3.0 MIN 0.5 MIN + 0.4 3.7 - 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-8P-01 DIP008-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS -9- 0.5 0.2 |
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